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u2734b preliminary information rev. a1, 24-jun-99 1 (13) fractional-n frequency synthesizer for dab tuner description the u2734b is a monolithic integrated fractional-n frequency synthesizer circuit fabricated with temic smiconductors' advanced uhf5s technology. designed for applications in dab receivers, it controls a vco to synthesize frequencies in the range of 70 mhz to 500 mhz in a 16-khz raster; four different reference divide factors can be selected. the lock status of the phase detector is indicated at a special output pin. three switching outputs can be addressed. a reference signal is generated by an on-chip reference oscillator. a frequency doubler provides an output signal at twice the frequency of the reference oscillator. two d/a converters at a resolution of 8 bit provide a digitally controllable output voltage. all functions of this ic are controlled by an i 2 c bus. electrostatic sensitive device. observe precautions for handling. features microprocessor-controlled via an i 2 c bus 4 addresses selectable reference oscillator reference frequency doubler (open-collector output) four reference divide factors selectable: 1024, 1120, 1152, 1536 effectively programmable 15-bit counter 1:2048 to 1:32767 effectively tristate phase detector with programmable charge pump superior phase-noise performance deactivation of tuning output programmable 3 switching outputs (open collector) 3 d/a converters (resolution: 8 bit) lock-status indication (open collector) block diagram 13bit counter 15054 programmable n/n+1 fractionaln control reference counte r 15bit latch 4bit latch switches mux mux 3bit latch tristate phase detector programmable charge pump 8bit latch 8bit latch osci 4 osco 5 d/a d/a vd 2 lock detector plck 3 pd 1 7 scl 6 adr 8 sda 16 swh 11 swc 13 cao 14 cbo 2bit latch 2bit latch frequency doubler x 2 rf 18 nrf 17 20 vs 19 gnd 10 fdo 9 nfdo 15 swg 8bit latch d/a 12 cco i 2 c-bus interface /control figure 1. block diagram
u2734b rev. a1, 24-jun-99 preliminary information 2 (13) ordering information extended type number package remarks u2734bbfs sso20 U2734B-BFSg1 sso20 taped and reeled according to iec 2683 pin description 1 2 3 4 5 6 7 8 10 9 20 18 19 17 12 11 swg cbo cao cco swc nrf swh rf gnd vs 16 15 14 13 14883 pd vd plck osci osco adr scl sda nfdo fdo figure 2. pinning pin symbol function 1 pd tristate charge pump output 2 vd active filter output 3 plck lock-indicating output (open collector) 4 osci input of reference oscillator/buffer 5 osco output of reference oscillator/buffer 6 adr address selection 7 scl clock (i 2 c) 8 sda data (i 2 c) 9 nfdo frequency-doubler output (inverted, open collector) 10 fdo frequency-doubler output (open collector) 11 swc switching output (open collector) 12 cco output of d/a converter c 13 cao output of d/a converter a 14 cbo output of d/a converter b 15 swg switching output (open collector) 16 swh switching output (open collector) 17 nrf rf input (inverted) 18 rf rf input 19 gnd ground 20 vs supply voltage
u2734b preliminary information rev. a1, 24-jun-99 3 (13) functional description the u2734b is a low-power fractional-n frequency syn- thesizer designed for applications in dab receivers. its rf operation range is 70 mhz to 500 mhz. as shown in the block diagram in figure 1, the device includes a reference oscillator, a reference divider, an input buffer for the rf divider, a programmable rf divider using fractional-n technique, a tristate phase detector, a programmable charge pump, four switching outputs, a frequency doubler for the reference signal, two d/a converters at a resolution of 8 bit and a control unit. the control unit has to be accessed by a microcontroller via the i 2 c bus. the device is mounted in an sso20 package. an appropriate application circuit is given in figure 8. the most striking feature of this circuit is the use of a special phase-noise shaping technique based on the frac- tional-n principle which concentrates the phase detector's phase-noise contribution to the spectrum of the controlled vco at frequency positions where it does not impare the quality of the received dab signal. a special property of the transmission technique which is used in dab is that the phase-noise weighting function (which measures the influence of the lo's phase noise to the phase information of the coded signal in a dab receiver) has zeros, i.e., if phase noise is concentrated in the position of such zeros as discrete lines, the dab signal is not impaired as long as these lines do not exceed a certain limit. for dab mode i, this phase-noise weighting function is shown in figure 3. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 df / hz pnwf figure 3. it is important to realize that this function shows zeros in all distances from the center line which are multiples of the carrier spacing. the technique of concentrating the phase noise in the positions of such zeros is protected by a patent. in this circuit, the phase detector is operated at a frequency which is four times the desired frequency raster spacing (e.g. 16 khz in case of dab) and the well-known fractional-n technique is used to synthesize the raster. as a result of this technique, spurious in the vco's frequency spectrum (see figure 10) occur not only in multiples of the phase detector's input comparison frequency (64 khz) but also in multiples of the raster frequency (16 khz). as described above, for all dab modes these spurious are placed in spectral positions where the phase-noise weighting function is zero. therefore, no measures are necessary to suppress these lines. the phase-noise performance of this circuit is demonstrated in figure 9. reference oscillator an on-chip oscillator generates the reference signal which is fed to the reference divider. by applying a crystal externally, as shown in figure 6, this oscillator generates a highly stable reference signal. if an external reference signal is available, the oscillator can be used as an input buffer. in such an application as that shown in figure 7 the reference signal has to be applied to the pin osci and the pin osco must be left open. reference divider four different scaling factors, sf ref , of the reference divider can be selected by means of the bits rd1 and rd2 in the i 2 c bus instruction code: 256, 280, 288, and 384. starting from a reference oscillator frequency of 16.384 mhz/ 17.92 mhz/ 18.432 mhz/ 24.576 mhz, these scaling factors provide a frequency raster of 64 khz. by changing the division ratio of the main divider from n to n+1 in an appropriate way (fractional-n technique), this frequency raster is interpolated to deliver a frequency spacing of 16 khz according to the dab specification. so, effectively, the reference divide factors 1024, 1120, 1152 and 1536 can be selected. by setting the i 2 c-bus bit t a test signal representing the divided input signal can be monitored at the switching output swc. main divider the main divider consists of a fully programmable 13-bit divider which defines a division ratio n. the applied division ratio is either n or n+1 according to the setting of a special control unit. generally speaking, the scaling factors sf = n+k/4 can be selected where k = 0, 1, 2, 3. in this way, vco frequencies f vco = 4 (n+k/4) f ref /(4 sf ref ) can be synthesized starting from a reference frequency, f ref. . if we define sf eff = 4 n+k and sf ref,eff = 4 sf ref we have f vco = sf eff f ref / sf ref,eff ,
u2734b rev. a1, 24-jun-99 preliminary information 4 (13) where sf eff is defined by 15 bits. in the following, this circuit is described in terms of sf eff and sf ref,eff . sf eff has to be programmed via the i 2 c-bus interface. an effective scaling factor from 2048 to 32767 can be selected. by setting of the i 2 c-bus bit t, a test signal representing the divided input signal can be monitored at the switching output swf. when the supply voltage is switched on, both the reference divider and the programmable divider are kept in reset state till a complete scaling factor is written onto the chip. changes in the setting of the programmable divider become active when the corresponding i 2 c-bus trans-mission is completed. an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. this behavior allows smooth tuning of the output frequency without disturbing the controlled vco's frequency spectrum. phase comparator and charge pump the tristate phase detector causes the charge pump to source or to sink current at the output pin pd depending on the phase relation of its input signals which are provided by the reference and the main divider respectively. four different values of this current can be selected by means of the i 2 c-bus bits i50 and i100. by means of this option, for example changes of the loop characteristics due to the variation of the vco gain as a function of the tuning voltage can be reduced. the charge pump current can be switched off using the i 2 c- bus bit tri. a change in the setting of the charge pump current becomes active when the corresponding i 2 c-bus transmission is completed. as described for the setting of the scaling factor of the programmable divider, an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. this behavior allows a change in the charge-pump current without disturbing the controlled vco's frequency spectrum. a high-gain amplifier (output pin: vd) which is implemented in order to construct a loop filter, as shown in the application circuit, can be switched off by means of the i 2 c-bus bit os. an internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. if phase lock is detected, the open-collector output pin plck is set high (logical value!). it should be noted that the output current of this pin must be limited by an external circuit as it is not limited internally. if the i 2 c- bus bit tri is set high, the lock-detector function is deactivated and the logical value of the plck output is undefined. switching outputs four switching outputs, controlled by the i 2 c-bus bits swc, swd, swg, swh, can be used for any switching task on the front-end board. the currents of these outputs are not limited internally. they have to be limited by external circuitry. frequency doubler an internal frequency doubler provides a signal twice the frequency of the reference signal appearing at the input pins ref and nref. if the i 2 c-bus bit ofd = high, the current of its open-collector outputs fdo and nfdo is doubled. by means of the i 2 c-bus bit ofd, the frequency-doubler function can be switched off. as shown in figure 11 (integration in temic dab receiver concept), the output signal of the frequency doubler can be used to construct the lo signal of the if circuit (u2759b). d/a converters three d/a converters, a, b and c, offer the possibility to generate two output voltages at a resolution of 8 bits. these voltages appear at the output pins cao, cbo and cco. the converters are controlled via the i 2 c-bus interface by means of the control bits ca0, ..., ca7, cb0, ..., cb7 and cc0, ..., cc7 respectively as described in the chapter `i 2 c-bus instruction codes'. the output voltages are defined as v c o = v m /128 c j 2 j , = a, b, c; j = 0, .., 7 where v m = 2.5 v nominally. due to the rail-to-rail outputs of these converters, virtually the full voltage range from 0 to 5 v can be used. a common application of these converters is the digital synthesis of control signals for tuning of preselectors. i 2 c-bus interface via its i 2 c-bus interface, various functions can be controlled by a microprocessor. these functions are outlined in the following chapter `i 2 c-bus instruction codes' and `i 2 c-bus functions'. the programming information is stored in a set of internal registers. by means of the pin adr, four different i 2 c-bus addresses can be selected as described in the chapter `electrical characteristics'. in figure 4, the i 2 c-bus timing parameters are explained, figure 5 shows a typical i 2 c- bus pulse diagram.
u2734b preliminary information rev. a1, 24-jun-99 5 (13) table 1. i 2 c-bus instruction codes description msb lsb address byte 1 1 0 0 0 as1 as2 0 divider byte 1 0 rd1 rd2 x x n 14 n 13 n 12 divider byte 2 x x n 11 n 10 n 9 n 8 n 7 n 6 divider byte 3 x x n 5 n 4 n 3 n 2 n 1 n 0 control byte 1 1 1 0 os t tri i100 i50 control byte 2 ofd 2ifd swc x x x swg swh control byte 3 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 converter byte 1 1 0 x x x x x x converter byte 2 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 converter byte 3 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 i 2 c-bus functions as1, as2 define the i 2 c-bus address rd1, rd2 define the effective scaling factor of the reference divider: rd1 rd2 effective scaling factor 0 0 1120 1 0 1152 0 1 1024 1 1 1536 n i effective scaling factor (sf eff ) of the main divider sf eff = sum( n i 2 i ) os os = high switches off the tuning output t for t = high, reference signals describing the output frequencies of the reference divider and programmable divider are monitored at swc (reference divider) and swf (programmable divider) tri tri = high switches off the charge pump cai, cbi, cci define the setting of the two d/a converters a and b (i = 0, ..., 7) i50, i100 define the charge pump current i50 i100 charge-pump current (nominal) / a low low 50 high low 102 low high 151 high high 203 ofd ofd = high switches off the frequency doubler 2ifd 2ifd = high doubles the frequency doubler output current swa swa = high switches on the output current
u2734b rev. a1, 24-jun-99 preliminary information 6 (13) i 2 c-bus data transfer format: start adr ack stop the consists of a sequence of divider bytes, control bytes and converter bytes each followed by ack. divider byte i must be followed by divider byte i+1 (control byte 1 if i = 3) or the instruction set must be finished. control bytes and converter bytes have to be handled accordingly. examples: start adr ack db1 ack db2 ack db3 ack ctb1 ack ctb2 ack ctb3 ack cvb1 ack cvb2 ack cvb3 ack stop start adr ack cb1 ack cb2 ack stop however: start adr ack db1 ack cb1 ack stop is not allowed. description: start start condition stop stop condition ack acknowledge adr address byte dbi divider byte i (i = 1, 2, 3) ctbi control byte i (i = 1, 2, 3) cvbi converter byte i (i = 1, 2, 3) i 2 c-bus timing the values of the drawn periods are specified in the section `electrical characteristics'. more detailed infor- mation can be taken from application note 1.0 (i 2 c-bus description). please note: due to the i 2 c-bus specification, the msb of a byte is transmitted first, the lsb last. 15038 t buf t r t f t hdstat t hdsta t low t hddat t high t sudat t susta t sustp sda scl stop start start stop figure 4. i 2 c-bus timimg 12479 sda divider byte 3 ack control byte 1 ack control byte 2 ack stop scl address byte ack divider byte 1 divider byte 2 ack start ack sda scl figure 5. typical i 2 c-bus pulse diagram
u2734b preliminary information rev. a1, 24-jun-99 7 (13) absolute maximum ratings parameters symbol min. typ. max. unit supply voltage v s 0.3 +5.5 v rf input voltage (ac) v rf , v nrf 1 v pp reference input voltage (ac) v osci 1 v pp i 2 c-bus input / output voltage v scl , v sda 0.3 5.5 v sda output current i sda 5 ma address select voltage v adr 0.3 +5.5 v switch output voltage, open collector v swa 0.3 +5.5 v switch output current, open collector v swa 4 ma plck output voltage v plck 0.3 +5.5 v plck output current i plck 0.5 ma frequency-doubler output, open collector v fdo , v nfdo v s 1 5.5 v junction temperature t j 125 c storage temperature t stg 40 +125 c thermal resistance parameters symbol value unit junction ambient r thja 140 k/w operating range parameters symbol value unit supply voltage v s 4.5 to 5.5 v ambient temperature range t amb 40 to +85 c electrical characteristics test conditions: v s = 5 v, t amb = 25 c (if not otherwise stated) parameters test conditions / pins symbol min. typ. max. unit supply current pin vs supply current sw a = low, tri = low, plck = low, os = low, i50 = high, i100 = high, ofd = low, 2ifd = low i s 14.5 18.1 21.7 ma sw a = low, tri = low, plck = low, os = low, i50 = high, i100 = high, ofd = high, 2ifd = low i so 16.2 ma effective scaling factor of programmable divider sf eff 2048 32767 effective scaling factor of reference divider rd1 = low, rd2 = low rd1 = high, rd2 = low rd1 = low, rd2 = high rd1 = high, rd2 = high sf ref,eff 1120 1152 1024 1536 tuning step 17.920 mhz/ 18.432 mhz/ 16.384mhz/ 24.576mhz reference frequency f rast 16 khz
u2734b rev. a1, 24-jun-99 preliminary information 8 (13) electrical characteristics test conditions: v s = 5 v, t amb = 25 c (if not otherwise stated) parameters test conditions / pins symbol min. typ. max. unit rf input pin rf, nrf input frequency range v s = 4.5 v, t amb = 20 c f rf 70 500 mhz input sensitivity v rfs 10 20 mv rms maximum input signal v rfmax 300 mv rms input impedance differential z rf 200 vswr vswr rf 2 ref input pin osci input frequency range v s = 4.5 v, internal oscillator overdriven f ref 5 30 mhz input sensitivity internal oscillator overdriven v refs 50 mv rms maximum input signal internal oscillator overdriven v refmax 300 mv rms input impedance single ended z ref 2 || 2.5 k /pf phase detector pin pd charge-pump current i100 = high, i50 = high i pd4 160 203 240 a i100 = high, i50 = low i pd3 120 151 180 a i100 = low, i50 = high i pd2 80 102 120 a i100 = low, i50 = low i pd1 40 50 60 a tri = high i pd,tri 100 na effective phase noise *) i pd = 203 a l pd 163 dbc/hz lock indication pin plck leakage current v plck = 5.5 v i plck,l 10 a saturation voltage i plck = 0.5 ma v plck,sat 0.5 v frequency doubler pin fdo, nfdo output current v fdo = v nfdo = v s, 2ifd = low i fdol , i nfdol 0.4 0.5 0.6 ma pp v fdo = v nfdo = v s, 2ifd = high i fdoh , i nfdoh 0.8 1.0 1.2 ma pp minimum output voltage v s = 5 v v fdo , v nfdo 4 v switches pin swa leakage current v swa = 5.5 v i sw,l 10 a saturation voltage i swa = 4 ma v sw,sat 0.5 v address selection pin adr as1 = 0, as2 = 0 0 0.1 v s v as1 = 0, as2 = 1 open as1 = 1, as2 = 0 0.4 v s 0.6 v s v as1 = 1, as2 = 1 0.9 v s v s v *) the phase detector's phase-noise contribution to the vco's frequency spectrum refers to the operating frequency of the phase detector divided by 4 according to the fractional-n technique (regularly: 16 khz).
u2734b preliminary information rev. a1, 24-jun-99 9 (13) electrical characteristics test conditions: v s = 5 v, t amb = 25 c (if not otherwise stated) parameters test conditions / pins symbol min. typ. max. unit d/a converters pins cao, cbo, cco output voltage c 7 = high, c 0 ... c 6 = low, = a, b, c v m 2.4 2.5 2.6 v variation of v m v s = 4.5 v to 5.5 v v m , v s 15 15 mv t amb = 40 to +85 c v m,temp 15 mv dynamic range |v c o n v m /128| 40 mv, |v cbo m v m /128| 40 mv, n = c j 2 j , = a, b, c v ll , v ul 0.5 4.5 v maximum output current | v c o | 10 mv, 0.5 v v c o , 4.5 v, = a, b, c i cao,max , i cbo,max 20 a i 2 c bus pins scl, sda input voltage scl/sda high v h 3 5.5 v low v l 1.5 v output voltage sda (open collector) i sda = 2 ma, sda = low v sda 0.4 v scl clock frequency f scl 0.1 100 khz rise time (scl, sda) t r 1 s fall time (scl; sda) t f 300 ns time before new transmission can start t buf 4.7 s scl high period t high 4 s scl low period t low 4.7 s hold time start t hdsta 4 s set-up time start t susta 4.7 s set-up time stop t sustp 4.7 s hold time data t hddat 0 s set-up time data t sudat 250 ns application circuits of reference oscillator 15041 osci osco 33p 68p 18p reference divider figure 6. oscillator operation 15042 osci osco reference divider 1n reference signal 50 figure 7. oscillator overdriven
u2734b rev. a1, 24-jun-99 preliminary information 10 (13) application circuit 15055 20 19 18 17 16 15 14 13 12 11 12345678910 u2734b 1n +8.5v l1 47nh (5%) l2 47nh (5%) 180p (1%) 27p (1%) (18p) l1, l2: ll1608f47nj (toko) 1n 1n u2759b/ u2735b 47k 4.7n 470p +8.5v 22k 1k 10n 1k 10n sda scl address select voltage bc846b 22k +5v v s 15p (5%) 600ens 9272y (toko) band switches u2750b vco signal tuning voltage alternative load circuit for f res = 36mhz v s m c +8.5v 1n preselectors 100n 100n 33p 18p 68p 100n figure 8. phase-noise performance (example: sf eff = 16899, sf ref,eff = 1120, f ref = 17.92 mhz, i pd = 200 a, spectrum analysis: hp70000, as application circuit above) center 270.384 mhz span 10.00 khz rb 100 hz vb 100 hz st 3.050 sec < 70 dbc/hz 10.00 db/div figure 9. center 270.384 mhz span 200.0 khz 10.00 db/div rb 1.00 khz vb 1.00 khz st 600.0 msec figure 10.
u2734b preliminary information rev. a1, 24-jun-99 11 (13) integration in temic dab receiver concept 12483 vco agc u2750b pll u2733b saw agc u2759b fsync generation pin ~ 190 ... 230 mhz l-band down-converter 79 ... 240 mhz 38.912 mhz 35.84 mhz 17.92 mhz dcxo system controller channel decoder afc if2 (if3) 3.072 mhz reference (u2734b) 1452 ... 1492 mhz figure 11. dab receiver frontend
u2734b rev. a1, 24-jun-99 preliminary information 12 (13) package information 13007 technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 110
u2734b preliminary information rev. a1, 24-jun-99 13 (13) ozone depleting substances policy statement it is the policy of temic semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. temic semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2 . class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency ( epa ) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c ( transitional substances ) respectively. temic semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use temic semiconductors products for any unintended or unauthorized application, the buyer shall indemnify temic semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. temic semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 ( 0 ) 7131 67 2594, fax number: 49 ( 0 ) 7131 67 2423

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